Samsung to Introduce SAINT: A 3D AI Chip Packaging Technology to Compete with TSMC

Samsung Electronics Co. has announced its plans to unveil an advanced three-dimensional (3D) chip packaging technology in the coming year. This move aims to rival Taiwan Semiconductor Manufacturing Company (TSMC), a dominant force in the foundry industry.

SAINT: Samsung's Cutting-Edge Interconnection Technology

KED Global reported that The Suwon-based chipmaker will utilize SAINT, or Samsung Advanced Interconnection Technology, to integrate memory and processors necessary for high-performance chips, including AI chips. The innovation allows for much smaller chip sizes, revolutionizing the industry notes ISP.

Under the umbrella of the SAINT brand, Samsung will introduce three types of advanced packaging technologies. SAINT S, the first type, involves the vertical stacking of SRAM memory chips and the CPU. SAINT D, the second type, integrates processors like the CPU and GPU with DRAM memory in a vertical packaging format. Lastly, SAINT L stacks application processors (APs), pushing the boundaries of current chip design.

Validation tests have already been conducted on some of Samsung's new technologies, including SAINT S. Following further tests with clients, Samsung plans to launch commercial services in the following year, solidifying its position in the advanced packaging market.

Significance of Packaging in Semiconductor Manufacturing

Packaging, the final step in semiconductor manufacturing, plays a critical role. It not only protects chips from corrosion but also facilitates the integration and connection of different chip types. Enhancing performance and enabling the merging of multiple devices, and packaging is central to technological advancements in the industry.

TSMC, Samsung, and Intel Corp. are engaged in fierce competition for dominance in advanced packaging. By integrating different semiconductors or vertically interconnecting multiple chips, advanced packaging paves the way for more streamlined and efficient electronic devices.

Advanced chip packaging is expected to witness significant growth, with the global market projected to reach $66 billion by 2027, according to consulting firm Yole Intelligence. Within this market, 3D packaging is anticipated to account for approximately a quarter, translating to $15 billion.

Presently, the mainstream approach to packaging is the 2.5D format, which aims to minimize data bottlenecks by placing chips near each other.

TSMC's Investment in 3D Inter-Chip Stacking Tech

To maintain its competitive edge, TSMC is heavily investing in its 3D inter-chip stacking technology, SoIC. This investment will benefit TSMC's clients, including tech giants such as Apple Inc. and Nvidia Corp. With an investment of 90 billion dollars, TSMC aims to solidify its position as a frontrunner in the semiconductor industry.

Unlike the challenges associated with shrinking the nanometer through ultra-fine processing, advanced packaging serves as a compelling alternative to boost semiconductor performance. This approach saves both time and addresses complex technological obstacles.

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